Device Structure . D$ W, B. i @$ w
◆ CMOS image sensor 7 \8 ~6 \% g# ^; g& M
◆ Image size Diagonal 11.1 mm (Type 2/3) Approx. 5.07 M pixels All-pixel Diagonal 7.7 mm (Type 1/2.35) Approx. 2.11 M pixels 1080p-Full HD , j3 s$ O. o3 z/ M" G: v: a
◆ Total number of pixels 2464 (H) × 2066 (V) Approx. 5.09 M pixels T5 O0 ]" L+ V
◆ Number of effective pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels 5 t$ }8 R$ |; r0 \
◆ Number of active pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels 6 U: J8 S$ u9 W0 D( }0 U, ^
◆ Number of recommended recording pixels 2448 (H) × 2048 (V) Approx. 5.01 M pixels All-pixel 1920 (H) × 1080 (V) Approx. 2.07 M pixels 1080p-Full HD 4 K7 ^, m: {% j/ x7 I9 a: E3 h9 z3 Z
◆ Unit cell size 3.45 µm (H) × 3.45 µm (V)
- Y9 j! O( P/ R2 L◆ Optical black Horizontal (H) direction: Front 0 pixels, rear 0 pixels Vertical (V) direction: Front 10 pixels, rear 0 pixels
" W6 k& {" A! g4 }◆ Substrate material Silicon
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7 w) S2 x% X0 z7 {Features
" V) m# ~* Q5 _8 t+ p5 R◆ CMOS active pixel type dots `6 m3 O, a' j' U l/ `4 v
◆ Built-in timing adjustment circuit, H/V driver and serial communication circuit
. I3 k; p5 m, q; `◆ Global shutter function
& f5 M' x# {% W' r1 ]# j◆ Input frequency 37.125 MHz / 74.25 MHz / 54MHz ( s1 q( Q6 ]% I' Z4 W
◆ Number of recommended recording pixels: 2448 (H) × 2048 (V) approx. 5.01 M pixels : r$ u# @( R+ G; f2 [/ ?9 `
Readout mode
7 i7 g) ?/ D$ Q( [All-pixel scan mode 8 _0 y1 O7 m8 l, [+ F. G8 T
1080p-Full HD readout mode / ^# y$ [. Y2 P4 m
Vertical / Horizontal 1 / 2 Subsampling mode ' C" ]9 {& _9 j4 O! x r
Vertical 2-pixel FD Binning mode ROI mode
' y! c0 J2 c1 ^; WVertical / Horizontal‐Normal / Inverted readout mode
! Q. X* a8 o! d/ ^1 Y x0 M◆ Readout rate 3 M( g* C( q+ h4 U& t
Maximum frame rate in
5 _9 d( c/ B9 [5 IAll-pixel scan mode: 8 bit 163.4 frame/s, 10 bit:144.7 frame/s, 12 bit:89.5 frame/s
2 O) h# m" p# Z( B◆ Variable-speed shutter function (resolution 1 H units) 0 R! g1 ~( w8 E; L4 T- X
◆ 8-bit / 10-bit / 12-bit A/D converter % t, Z6 g+ }: E; v
◆ CDS / PGA function 0 dB to 24 dB: Analog Gain (0.1 dB step) 24.1 dB to 48 dB: Analog Gain: 24 dB + Digital Gain: 0.1 dB to 24 dB (0.1 dB step) $ z+ |4 V& r% Y# s" s
◆ I/O interface Low voltage LVDS (150 mVp-p) serial (4 ch / 8 ch / 16ch switching) DDR output 1 o# A8 j2 g2 C' a: d
◆ Recommended lens F number: 2.8 or more (Close side)
, g: R3 j" H& v& D( y( H0 b; J◆ Recommended exit pupil distance: –100 mm to –∞
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|Shenzhen Lianshi Electronics Co., Ltd
( 粤ICP备13003189号 )
发表于 2022-3-29 21:22:13