Device Structure
0 `* ]' m! n7 B0 O◆ CMOS image sensor
. \3 L- |5 @9 E; e( ?0 E◆ Image size Diagonal 11.1 mm (Type 2/3) Approx. 5.07 M pixels All-pixel Diagonal 7.7 mm (Type 1/2.35) Approx. 2.11 M pixels 1080p-Full HD , _/ j7 ]# D- v: D6 f. n8 h
◆ Total number of pixels 2464 (H) × 2066 (V) Approx. 5.09 M pixels
* `- N# @' m! Z4 d1 D' K3 }" `* k◆ Number of effective pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels : k, l+ y. L! @. [
◆ Number of active pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels
2 E) B2 M6 P- W: m2 r◆ Number of recommended recording pixels 2448 (H) × 2048 (V) Approx. 5.01 M pixels All-pixel 1920 (H) × 1080 (V) Approx. 2.07 M pixels 1080p-Full HD
h% u6 R0 A1 Q' D( f◆ Unit cell size 3.45 µm (H) × 3.45 µm (V) % [: G4 A5 `) z1 w* ^
◆ Optical black Horizontal (H) direction: Front 0 pixels, rear 0 pixels Vertical (V) direction: Front 10 pixels, rear 0 pixels
, t3 u8 y) V$ Y |4 x0 w4 }( A◆ Substrate material Silicon* X; s w O6 t) a4 H; ^
7 d* ?/ v% Y* V
+ I5 c5 |3 ?5 F. }( OFeatures 0 z4 K1 }9 A) z# {3 J- A
◆ CMOS active pixel type dots 5 Z* k. e3 y0 A
◆ Built-in timing adjustment circuit, H/V driver and serial communication circuit
& m7 U9 o8 `, ]8 ~◆ Global shutter function ) ~0 I M5 j3 g7 j W1 [
◆ Input frequency 37.125 MHz / 74.25 MHz / 54MHz
/ v" s# F# t/ U0 d; N# E◆ Number of recommended recording pixels: 2448 (H) × 2048 (V) approx. 5.01 M pixels
" q* u# v& c2 d4 e; f; dReadout mode
$ n- R0 h4 H" h) BAll-pixel scan mode
3 j" m/ B1 Z: A( T1080p-Full HD readout mode
& x# z- u8 `1 yVertical / Horizontal 1 / 2 Subsampling mode 5 `! I) [$ ^" b* o
Vertical 2-pixel FD Binning mode ROI mode
" `/ q$ e( D% h* [) w- \8 }# B* |Vertical / Horizontal‐Normal / Inverted readout mode 6 P, c2 o) z( C
◆ Readout rate
" Q1 C% w3 c f& k7 hMaximum frame rate in * N% K6 Y$ B6 e5 `& s
All-pixel scan mode: 8 bit 163.4 frame/s, 10 bit:144.7 frame/s, 12 bit:89.5 frame/s
. X+ W% ]; m6 k$ B0 \◆ Variable-speed shutter function (resolution 1 H units) 1 H" z! K* L# k
◆ 8-bit / 10-bit / 12-bit A/D converter . l' u3 [: J1 l+ ^- V
◆ CDS / PGA function 0 dB to 24 dB: Analog Gain (0.1 dB step) 24.1 dB to 48 dB: Analog Gain: 24 dB + Digital Gain: 0.1 dB to 24 dB (0.1 dB step) 3 j) S9 h f2 x0 `
◆ I/O interface Low voltage LVDS (150 mVp-p) serial (4 ch / 8 ch / 16ch switching) DDR output
d' l4 j: U+ ?$ T◆ Recommended lens F number: 2.8 or more (Close side)
# U3 `; g+ W0 u! ~( m9 E◆ Recommended exit pupil distance: –100 mm to –∞
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|Shenzhen Lianshi Electronics Co., Ltd
( 粤ICP备13003189号 )
发表于 2022-3-29 21:22:13