Device Structure
1 l8 E. {3 j3 }! k. ~5 r◆ CMOS image sensor
w9 ]9 D3 S$ O- a◆ Image size Diagonal 11.1 mm (Type 2/3) Approx. 5.07 M pixels All-pixel Diagonal 7.7 mm (Type 1/2.35) Approx. 2.11 M pixels 1080p-Full HD
! H: y+ Y" t1 m: C9 `; H◆ Total number of pixels 2464 (H) × 2066 (V) Approx. 5.09 M pixels r5 q6 Q3 S; y6 y) U
◆ Number of effective pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels
/ u& G4 S3 @" X$ @9 v0 [+ L7 z◆ Number of active pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels ! q+ \9 B( t- Q- m* O; P
◆ Number of recommended recording pixels 2448 (H) × 2048 (V) Approx. 5.01 M pixels All-pixel 1920 (H) × 1080 (V) Approx. 2.07 M pixels 1080p-Full HD
" m. g! m$ m% b! v4 v◆ Unit cell size 3.45 µm (H) × 3.45 µm (V)
4 s( j; s" u9 U1 v8 ?. L7 g◆ Optical black Horizontal (H) direction: Front 0 pixels, rear 0 pixels Vertical (V) direction: Front 10 pixels, rear 0 pixels . V% V! ]) K1 s- i1 L5 o) x
◆ Substrate material Silicon4 [3 e% ~. Z; S& r) h6 A- ]; Y" d
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7 u' G# _$ d: }0 UFeatures
; P3 r( W. w, T3 W( n◆ CMOS active pixel type dots
4 X- S6 d+ i4 G( {2 h% r◆ Built-in timing adjustment circuit, H/V driver and serial communication circuit
& A+ K" V+ t' r# U3 U◆ Global shutter function
Y3 q+ l7 m" J: E, U◆ Input frequency 37.125 MHz / 74.25 MHz / 54MHz
- G# @- S3 u* f; h3 S◆ Number of recommended recording pixels: 2448 (H) × 2048 (V) approx. 5.01 M pixels
! q G; T% }7 y }% h+ x3 GReadout mode 4 { N/ t, X# ~- V/ H8 f9 V
All-pixel scan mode 9 J3 v" d+ E9 x+ Q" ^, A4 l3 {
1080p-Full HD readout mode
: [! U+ C2 i% E# R( }( ^Vertical / Horizontal 1 / 2 Subsampling mode 7 Q1 [5 }5 w) r& s% U. o
Vertical 2-pixel FD Binning mode ROI mode : a% F: g1 G, u6 O( x% q1 n
Vertical / Horizontal‐Normal / Inverted readout mode
& \& \1 B0 f- Q6 c; L" G◆ Readout rate
, m$ p1 s5 V; d& H$ \* JMaximum frame rate in , a5 W& v4 W! ^& X, s
All-pixel scan mode: 8 bit 163.4 frame/s, 10 bit:144.7 frame/s, 12 bit:89.5 frame/s
, x) E1 d1 s4 _◆ Variable-speed shutter function (resolution 1 H units)
: Z; F: U7 L( C' G◆ 8-bit / 10-bit / 12-bit A/D converter
. L& ]. Y `: c◆ CDS / PGA function 0 dB to 24 dB: Analog Gain (0.1 dB step) 24.1 dB to 48 dB: Analog Gain: 24 dB + Digital Gain: 0.1 dB to 24 dB (0.1 dB step)
& T+ E2 \$ t# g. Y◆ I/O interface Low voltage LVDS (150 mVp-p) serial (4 ch / 8 ch / 16ch switching) DDR output / z1 Q0 F/ m* n
◆ Recommended lens F number: 2.8 or more (Close side) - g2 L' Y- b, s- @" z0 s3 A
◆ Recommended exit pupil distance: –100 mm to –∞
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|Shenzhen Lianshi Electronics Co., Ltd
( 粤ICP备13003189号 )
发表于 2022-3-29 21:22:13