Device Structure
# y9 b5 h$ f# h I5 j◆ CMOS image sensor
( ]9 D4 B7 i+ L/ g◆ Image size Diagonal 11.1 mm (Type 2/3) Approx. 5.07 M pixels All-pixel Diagonal 7.7 mm (Type 1/2.35) Approx. 2.11 M pixels 1080p-Full HD 5 T2 C4 n% {6 `8 ^
◆ Total number of pixels 2464 (H) × 2066 (V) Approx. 5.09 M pixels
2 q3 ~7 }' ^) f! Q; | _8 Q1 X, g◆ Number of effective pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels
5 J' [" }9 ?2 M" A◆ Number of active pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels
! q/ N: b/ ^1 K k$ h3 m2 t: `# D◆ Number of recommended recording pixels 2448 (H) × 2048 (V) Approx. 5.01 M pixels All-pixel 1920 (H) × 1080 (V) Approx. 2.07 M pixels 1080p-Full HD - L2 m; D% |9 z0 e6 G. U5 t
◆ Unit cell size 3.45 µm (H) × 3.45 µm (V)
+ }+ a; i) F& S0 h' o& }◆ Optical black Horizontal (H) direction: Front 0 pixels, rear 0 pixels Vertical (V) direction: Front 10 pixels, rear 0 pixels $ {5 `' V. ?1 k' Y
◆ Substrate material Silicon
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Features 7 n! B: y8 E) \% g/ @
◆ CMOS active pixel type dots
( h; \1 w( Z4 ~ m4 i5 ]8 y1 F$ ~◆ Built-in timing adjustment circuit, H/V driver and serial communication circuit
% F+ ], O& |* M3 J◆ Global shutter function
. g- \$ w' G5 `. V◆ Input frequency 37.125 MHz / 74.25 MHz / 54MHz % S9 O3 A0 \* _ f0 l5 l
◆ Number of recommended recording pixels: 2448 (H) × 2048 (V) approx. 5.01 M pixels A5 w& M; c: y/ j. {
Readout mode $ D0 J" |, u+ d5 `1 c, J* {
All-pixel scan mode
. q8 j, C% ~+ m8 @1080p-Full HD readout mode
* s5 m, }( i2 z0 W2 X0 }Vertical / Horizontal 1 / 2 Subsampling mode
& v6 _1 f) D7 `7 O) f: [Vertical 2-pixel FD Binning mode ROI mode
Y% Z/ L4 _2 U8 [9 D9 N3 [Vertical / Horizontal‐Normal / Inverted readout mode ) k/ a8 t: |. k
◆ Readout rate & S/ G( @. n8 d, d( ^
Maximum frame rate in / K% W6 P* ?- h& B
All-pixel scan mode: 8 bit 163.4 frame/s, 10 bit:144.7 frame/s, 12 bit:89.5 frame/s 5 u n8 X+ Y2 S T8 e6 z# v
◆ Variable-speed shutter function (resolution 1 H units)
9 a9 A# K" T# D4 ^: ]◆ 8-bit / 10-bit / 12-bit A/D converter 6 \* y4 _' l6 A
◆ CDS / PGA function 0 dB to 24 dB: Analog Gain (0.1 dB step) 24.1 dB to 48 dB: Analog Gain: 24 dB + Digital Gain: 0.1 dB to 24 dB (0.1 dB step)
) j) e8 Q% V" q% Y0 [: g6 q0 Y◆ I/O interface Low voltage LVDS (150 mVp-p) serial (4 ch / 8 ch / 16ch switching) DDR output
( v, z( B( N' \◆ Recommended lens F number: 2.8 or more (Close side)
0 F7 E" _6 P, Z) D+ b/ o# H◆ Recommended exit pupil distance: –100 mm to –∞
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|Shenzhen Lianshi Electronics Co., Ltd
( 粤ICP备13003189号 )
发表于 2022-3-29 21:22:13