Device Structure
1 a1 z9 x; a5 \◆ CMOS image sensor
1 Y. D1 x Y& v2 P0 p* w: [◆ Image size Diagonal 11.1 mm (Type 2/3) Approx. 5.07 M pixels All-pixel Diagonal 7.7 mm (Type 1/2.35) Approx. 2.11 M pixels 1080p-Full HD 7 X8 d# V3 O* M ^) B3 t
◆ Total number of pixels 2464 (H) × 2066 (V) Approx. 5.09 M pixels
8 A% ?5 x( D- a/ Y◆ Number of effective pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels % q$ Z2 @8 Z1 D G- I1 ]% z
◆ Number of active pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels 4 V) k- r4 ?- Z" l z( k
◆ Number of recommended recording pixels 2448 (H) × 2048 (V) Approx. 5.01 M pixels All-pixel 1920 (H) × 1080 (V) Approx. 2.07 M pixels 1080p-Full HD
, X% n# _5 P+ }; W: _7 g◆ Unit cell size 3.45 µm (H) × 3.45 µm (V)
. X' c& z4 O- P7 q* e( p# b◆ Optical black Horizontal (H) direction: Front 0 pixels, rear 0 pixels Vertical (V) direction: Front 10 pixels, rear 0 pixels 7 W& {% H1 j) o" E+ z# s. e* i
◆ Substrate material Silicon* T4 @0 S+ t% E4 K
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Features
9 M! p1 A7 Z- C% ~# G◆ CMOS active pixel type dots * _$ k" \1 j r( ] J
◆ Built-in timing adjustment circuit, H/V driver and serial communication circuit 4 p9 T, i4 U6 ~8 T. E# L
◆ Global shutter function 3 q# T" Z6 v {; [5 \5 O0 C
◆ Input frequency 37.125 MHz / 74.25 MHz / 54MHz N( G! c/ N% n5 q9 ^8 t
◆ Number of recommended recording pixels: 2448 (H) × 2048 (V) approx. 5.01 M pixels
1 o2 \- y3 o j' x7 F: w5 Y) sReadout mode
! ]) E; W. r9 O& CAll-pixel scan mode 7 x- K! x& l* W" P
1080p-Full HD readout mode
$ Z; g# s& |# eVertical / Horizontal 1 / 2 Subsampling mode " g# g7 i6 Y& H: R- _8 u+ I3 L
Vertical 2-pixel FD Binning mode ROI mode ( a) @4 R2 J% e# p3 a- _8 h/ I
Vertical / Horizontal‐Normal / Inverted readout mode 9 |; `: z' T; N6 `4 b' @* j
◆ Readout rate 7 d( E2 H9 }/ N' ^# P
Maximum frame rate in 6 a9 M4 O! t7 E; w& [) e4 L+ a H! Y
All-pixel scan mode: 8 bit 163.4 frame/s, 10 bit:144.7 frame/s, 12 bit:89.5 frame/s
% ~" }5 r9 v+ L* _◆ Variable-speed shutter function (resolution 1 H units) 8 `! W% C; Q' p V2 W6 \
◆ 8-bit / 10-bit / 12-bit A/D converter
+ E( f" S+ g0 p& w4 E◆ CDS / PGA function 0 dB to 24 dB: Analog Gain (0.1 dB step) 24.1 dB to 48 dB: Analog Gain: 24 dB + Digital Gain: 0.1 dB to 24 dB (0.1 dB step) + b; } J4 N$ d& i- D
◆ I/O interface Low voltage LVDS (150 mVp-p) serial (4 ch / 8 ch / 16ch switching) DDR output
( Y& r, P; X: U+ g) I( K, T- \◆ Recommended lens F number: 2.8 or more (Close side)
# Q, R; x( E+ V6 v. R4 B5 ]2 Y* \◆ Recommended exit pupil distance: –100 mm to –∞+ k9 i* L) w% _* o3 R
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|Shenzhen Lianshi Electronics Co., Ltd
( 粤ICP备13003189号 )
发表于 2022-3-29 21:22:13